الاسم : محمد عبد علي جودة
العنوان : مدرس
الكلية : الهندسة
القسم : هندسة الحاسبات
mohammed.joudah@uobasrah.edu.iq : الايميل
العنوان : مدرس
الكلية : الهندسة
القسم : هندسة الحاسبات
mohammed.joudah@uobasrah.edu.iq : الايميل
| رابط Google Scholar: | https://scholar.google.com/citations?hl=en&user=yFKaSuYAAAAJ&authuser=1 |
|---|---|
| رابط Research Gate : | https://www.researchgate.net/profile/Mohammed_Al-Ebadi |
| رابط Web of Science : | https://publons.com/researcher/3324205/mohammed-al-ibadi/ |
| رابط Scopus : | https://www.scopus.com/authid/detail.uri?authorId=57218587722 |
| رابط ORCID : | https://orcid.org/0000-0002-1034-3475 |
| عنوان البحث | النوع | الناشر | السنة | عالمي | مفرد | ثومبسون رويتر (كلارفيت) |
سكوبس | تحميل |
|---|---|---|---|---|---|---|---|---|
| Fast combined decimal/ binary multiplier based on redundant BCD 4221-8421 digits recoding | بحث مجلة | (Iraqi Journal for Electrical and Electronic Engineering (IJEEE | 2017 |
|
||||
| A New Hardware Architecture for Fuzzy Logic System Acceleration | بحث مجلة | (Iraqi Journal for Electrical and Electronic Engineering (IJEEE | 2016 |
|
||||
| Design and Implementation of A Novel FPGA-Based Pipelined-Parallel Processor Architecture for Shortest Path Search. | بحث مؤتمر | Proceedings of The Second Engineering Scientific Conference of University of Mosul, College of Engineering | 2013 |
|
||||
| A New Hardware Architecture for Parallel Shortest Path Searching Processor Based-on FPGA Technology. | بحث مجلة | (International Journal of Electronics and Computer Science Engineering (IJECSE | 2012 |  |
|
|||
| Algorithm For 2D-Data Array Addition Using Digit-Decomposition-Plane Representation | بحث مجلة | (Iraqi Journal for Electrical and Electronic Engineering (IJEEE | 2007 |
|
||||
| High Speed Parallel Optical Adder for Quaternary Signed-Digit Number Using Digit-Decomposition-Plane Representation | بحث مجلة | (J. Basrah Researches (Sciences | 2006 |
|
||||
| FPGA Based Hierarchical Fuzzy System | بحث مؤتمر | IEEE | 2020 | |
|
|||
| Hardware Implementation for High-Speed Parallel Adder for QSD 2D Data Arrays | بحث مؤتمر | IEEE | 2020 | |
|
|
||
| Design of High Precision Radix-8 MAF Unit with Reduced Latency | بحث مؤتمر | IEEE | 2020 | |
|
|||
| FPGA Design of Image Encryption and Decryption using Chua’s Chaotic Masking | بحث مجلة | International Journal of Electrical and Computer Engineering, IJECE, Accepted Jul 18, 2021 | 2021 | |
|
|||
| Implementation of Chaotic System Using FPGA | بحث مؤتمر | 2021 6th Asia-Pacific Conference on Intelligent Robot Systems (ACIRS 2021) July 16-18, 2021 – Japan, Tokyo | 2021 | |
|
|||
| New Artificial Neural Network Design for Chua's Chaotic System Prediction Using FPGA Hardware Co-Simulation | بحث مجلة | International Journal of Electrical and Computer Engineering, IJECE, Accepted May 8, 2021 | 2021 | |
|